(r2) SequentialSignal < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>SequentialSignal (revision 2) (raw view)~~EditAttach~~
---+ Sequential Signal Declarations

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---++ Proposal Editing Information
   * Who Updates: Main.JimLewis, &lt;Add YourName &gt;, ...
   * Date Proposed: 2012-08-19
   * Date Last Updated: 2012-08-19
   * Priority:
   * Complexity:
   * Focus: Testbench
---++ Requirement Summary

Declarations of signals in subprograms and processes.

Chaining together transaction based subprograms that have signal IO. Signal as a local in a clocked process - flip-flop example.
---++ Related and/or Competing Issues: none
---++ Use Model:

alias to external name that is a signal cannot be done in a process. 

In a simple testbench with a DUT and driven by processes, where can we put an alias to an external name reference. It would be convenient to put it in a process, but current language would require it to be in a block statement. It cannot go in the architecture declaration since the DUT has not been elaborated yet. 

---++ Proposal

---++ Questions

---++ General Comments

14.7 Dynamic elaboration

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NOTE 1—It is a consequence of these rules that declarative items appearing within the declarative part of a subprogram body are elaborated each time the corresponding subprogram is called; thus, successive elaborations of a given declarative item appearing in such a place may create items with different characteristics. For example, successive elaborations of the same subtype declaration appearing in a subprogram body may create subtypes with different constraints.

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It doesn't seem possible to dynamically elaborate signals. It would be a terrible simulator complication to be able to add or remove signals and queues from an elaborated design model dynamically.

A process statement (a procedure, not a function which is an expression) communicating to the process through signals requires a process statement that implies hierarchy (a block statement) and promotion of a sequential procedure statement to a concurrent procedure statement.. We already have under utilized block statements. This doesn't appear to be something VHDL needs to support and would require devolving such process statements into block statements and process statements for simulation, essentially expressing that level of hierarchy you're trying to imply but avoid.

-- Main.DavidKoontz - 2014-12-04
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---++ Supporters

_Add your signature here to indicate your support for the proposal_

-- Main.JimLewis - 2014-12-04

---++ Against

-- Main.DavidKoontz - 2014-12-04
Topic revision: r1 - 2020-02-17 - 15:34:59 - TWikiGuest
P1076/Ballots