(r2) MultiCyclePath < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>MultiCyclePath (revision 2) (raw view)~~EditAttach~~

---+ Multicycle Path

%TOC%

---++ Proposal Information
   * Current Owner: None, ...
   * Contributors: None, ...
   * Date Proposed: 2014-June-22
   * Date Last Updated: 2014-June-22
   * Priority:
   * Complexity:
   * Focus: RTL
   * Related Issues: None
   * Competing Issues: None
---++ Requirement Summary

Speciification of multi-cycle paths in language syntax and works for both simulation and synthesis.

Perhaps capture false paths as well and simulate them

See ISAC [[http://www.eda.org/isac/IRs-VHDL-2002/IR2003.txt][IR2003]]

---++ Related Issues

[[ClockedShorthand]] offers several proposed syntax examples to describe multicycle paths.

[[TimingConstraints]] proposes the ability to be able to describe timing constraints from within VHDL (including multicycle paths and false paths).

---++ Some initial thoughts that are going no where

For a simulation, a multicycle path with 4 clock delays can be specified with the following, however, this will not help with simulation
<verbatim>
process (Clk) 
begin
  if rising_edge(Clk) then 
    AReg <= transport 'X', A after 3 * tperiod_Clk + tpd; 
  end if ; 
end process ; 
</verbatim>

---++ Implementation

TBD What would be better is to use PSL

---++ Comments

---++ Supporters

Topic revision: r1 - 2020-02-17 - 15:34:56 - TWikiGuest

P1076/Ballots