TWiki
>
P1076/Ballots Web
>
Vhdl2019CollectedRequirements
>
CrossLanguageInstances
(2020-02-17,
JimLewis
)
(raw view)
E
dit
A
ttach
---+ Foreign / Cross Language Model Instances %TOC% ---++ Proposal Editing Information * Who Updates: . * Date Proposed: * Date Last Updated: * Priority: * Complexity: * Focus: Testbench ---++ Requirement Summary * Env 1, 4: Foreign / Cross Language Model Instances * Type mapping per DPI proposal * Formalize what tools are already doing. * What types need to be exchanged between SV and VHDL? ---++ Proposal ---++ Rationale ---++ Related and/or Competing Issues: None ---++ Use Model: ---++ Questions ---++ General Comments -- Main.ErnstChristen - 2015-01-27 I don't see this as an issue to be addressed by VHDL. ---++ Supporters _Add your signature here to indicate your support for the proposal_
E
dit
|
A
ttach
|
P
rint version
|
H
istory
: r3
<
r2
<
r1
|
B
acklinks
|
V
iew topic
|
Ra
w
edit
|
M
ore topic actions
Topic revision: r3 - 2020-02-17 - 15:34:52 -
JimLewis
P1076/Ballots
Log In
or
Register
P1076/Ballots Web
Create New Topic
Index
Search
Changes
Notifications
RSS Feed
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2026 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback