ComponentDerivedFromEntity < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>ComponentDerivedFromEntity (2020-02-17, JimLewis) (raw view)EditAttach
---+ Component Declaration Derived from an Entity Declaration

%TOC%

---++ Proposal Editing Information
   * Who Updates: Open
   * Transcribed by: Main.JimLewis
   * Date Proposed: 2014-04-03
   * Date Last Updated: 2014-04-03
   * Priority:
   * Complexity:
   * Focus: Any
   * Recommended Action: Reject

---++ Requirement Summary

[[http://www.eda.org/isac/IRs-VHDL-2002/IR2011.txt][ISAC IR 2011]]. Request syntax that creates a component declaration from an entity decalaration and puts it into a specified package.

---++ Problem Description

Translated by [[Main.JimLewis][Jim Lewis]]. They are putting components in packages and noting when more than one component is in a package it is difficult. Furthermore if you put just one component in a package, then why not a short hand prior to the entity that creates a component for that entity in a named package.

---++ Related and/or Competing Issues: none

---++ Proposal

Use the following syntax to imply a component in a package:
<verbatim>use IEEE.std_logic_1164.all;
go_into_package MyDesign;
entity subcomponent ...end subcomponent;
architecture x of subcomponent is ... end x;
</verbatim>

A simple translation of this is that the "go_into_package" is a short had replacing the first 4 lines below:
<verbatim>use IEEE.std_logic_1164.all;                    \
package MyDesign is                             |  These 4 lines = "go_into_package"
  component subcomponent ...end subcomponent;   |
end package MyDesign ;                          /

use IEEE.std_logic_1164.all;
entity subcomponent ...end subcomponent;
architecture x of subcomponent is ... end x;
</verbatim>

What it really seems they are asking for though is a way to include numerous components into a single package this way, however, this will not solve their stated compilation issues.

A looser translation of this last item, which would solve their compilation issues, is to have a way to reference numerous separate packages under one name, such as the context declaration included as part of VHDL-2008.
---++ Use Models

---++ Arguments against
---+++ An equivalent feature exists in VHDL-93

VHDL-93 introduced direct entity instantiation. This allows one to forgo the necessity to create a component declaration.

Issues with direct entity instantiation:
   * At the time of the proposal (and maybe still), this was not implemented by all synthesis tools. 
      * This cannot be a consideration as any new syntax can potentially have the same issues.
   * The architecture in a direct entity instantiation is not configurable 
      * We have a proposal for this. See [[ConfigureDirectInstantiation]]
---+++ A suitable methodology exists
   1 Put each component in a separate package. As the OP noted, putting all components into a common package results in large compilations.
   1 Generate the package by either:
      * Manually capture it before the entity (as shown in the interpretation of "goes_into_package" in the proposal).
      * Write a script that generates the component in a package with a name that is algorithmicly related to the component name, such as subcomponent_CompPkg.
   1 Use VHDL-2008 context declarations to collect the *_CompPkg under one name.
<verbatim>context chip1_CompPkg is
   library chip1_lib;
     use chip1_lib.Comp1_CompPkg.all;
     use chip1_lib.Comp2_CompPkg.all;
     . . . 
     use chip1_lib.CompN_CompPkg.all;
end context chip1_CompPkg ;
</verbatim>

---++ General Comments

---++ Supporters

_Add your signature here to indicate your support for the proposal_&lt;/verbatim&gt;
Topic revision: r2 - 2020-02-17 - 15:34:52 - JimLewis
P1076/Ballots