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---+ Links to proposals etc.

[[VerilogAMS.BackAnnotationProposal][Back annotation (fairly language neutral)]]

[[%PUBURL%/VerilogAMS/DiscreteAnalogModelingInSV/3398-alt.pdf][Alternative scheme for nettypes (Sysytem Verilog)]]

VHDL proposals -

[[http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/Vhdl2019CollectedRequirements#Proposal_Summary_Link_to_Proposa][P1076.Vhdl2019CollectedRequirements#Proposal_Summary_Link_to_Proposa]]

C++ Extension (if you are fed up with EDA companies) -

[[http://parallel.cc]]

-- %USERSIG{KevinCameron - 2016-03-11}%

---++ Comments

%COMMENT%

Topic revision: r3 - 2020-02-17 - 15:34:49 - JimLewis

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