The following lists the sections with the Verilog-AMS 2.3.1 document. Each section needs to be reviewed to identify the work required to merge into the SystemVerilog document. There are currently 11 sections without any owner.

1. Verilog-AMS introduction

Owner: David Miller
Editor's Comments: Changing this based on our decision to go ahead with a very shallow integration. Most of the changes in this section simply reflect different references. However it is important that we agree on this chapter as it sets the overall tone for the rest of the document merge. All page references are to Verilog-AMS 2.3.1

Document: 01-intro.pdf

Identified Changes:

• Change section heading to 'Introduction'
• Replace all references to Verilog-AMS with SystemVerilog-AMS
• Replace all references to 1364-2005 Verilog with P1800-2009 SystemVerilog
• 1.1 Overview
  
  • Para1:
    Start sentence with 'The'
    At end of paragraph, add: Accellera is a consortium of EDA, semiconductor, and system companies.
  • Para2
    Reword: SystemVerilog-AMS HDL consists of the complete IEEE std P1800-2009 SystemVerilog HDL specification, as well as the Verilog-AMS 2.3.1 HDL, and extensions to both for specifying the full SystemVerilog-AMS HDL.
  • Insert para: SystemVerilog is a unified hardware design, specification, and verification language based on the Accellera System Verilog 3.1a extensions to the IEEE std 1364 Verilog HDL.
• Aside from these initial changes and global replace of Verilog-AMS with SystemVerilog-AMS, 1364-2005 Verilog with P1800-2009 SystemVerilog there are very few other changes. The rest of the chapter deals with simulating a conservative system (analog) which won't change with SystemVerilog-AMS

2. Lexical conventions

Owner: David Miller
Editor's Comments: I am not going to correct reference hyperlinks. It is easier to do a pass through the document once all the sections are in place to fix these.
The grammar for the Numbers section needs to be updated to reflect the merged grammar.
I don’t mention casting in the Real literal constants section
I don’t discuss array assignment patterns or how to determine the type (implicit or explicit) of an array literal
2.6.3 - syntax for system tasks and system functions needs to be updated to reflect current merged grammar

Document: 02-lexical.pdf

Identified Changes:

3. Data types

Owner: Martin O'Leary

4. Expressions

Owner: David Miller

5. Analog behavior

Owner: David Miller

6. Hierarchical structures

Owner: Marq Kole

7. Mixed signal

Owner: Martin O'Leary

8. Scheduling semantics

Owner: orhpan

9. System tasks and functions

Owner: Martin O'Leary

10. Compiler directives

Owner: orhpan

11. Using VPI routines

Owner: orhpan

12. VPI routine definitions

Owner: orhpan

Annex A Formal syntax definition

Owner: Graham Helwig

An initial pass at a merge grammar has been completed and can be found at: annexA_bnf_merged_v3.pdf

Annex B List of keywords

Owner: Graham Helwig

A document containting the merged keyword for Verilog-AMS and SystemVerilog can be found at: Merged Keywords

Annex C Analog language subset

Owner: orhpan

Annex D Standard definitions

Owner: orhpan

Annex E SPICE compatibility

Owner: orhpan

Annex F Discipline resolution methods

Owner: orhpan

Annex G Change history

Owner: orhpan

Annex H Glossary

Owner: orhpan

-- DavidMiller - 2011-01-27