Hi Brent, > For external variable names, we can only reference shared variables. > > Apart from the issues of mutual exclusion for accesses, does anyone know of any other reasons why we shouldn't allow references to standard variables within processes? > > When using external names for grey box access in a verification environment, the one thing that is still inaccessible are memory arrays coded as standard variables. > > Can we add this in as a requirement with the proviso that the user is responsible for controlling mutual accesses in the same way as shared variables had to be used pre VHDL2002? Perhaps this is a reason to code your memory arrays as a shared variable. :) Do you have other things that you would like to access. One of the next release candidates for some of the open source work I am doing (OSVVM.org), is our protected type based package for memory models. Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jun 6 10:53:31 2014
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