Hi Lieven, > Something that I miss in these proposals is a way to generically convert any record into a std_logic_vector (and make that part of the standard library). Would it be possible to define a function > attribute on types (user defined, but for the standard types part of the standard library) and use that attribute to do the conversion? That is an interesting problem. Would you allow the record to contain integers, real, ... or would you limit it to contain only types, arrays, or composites that are built from the std_ulogic family? It would be challenging if you allow things other than the std_ulogic family as how would you size integers - sure it is easy for one integer in the record, but for multiple, it would be a challenge. There is a record specific example of to_vector in http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/RecordIntrospection If the record only contained std_ulogic family perhaps this could be extended. There is no reason to make DATA_T_VECTOR_LENGTH a constant (other than it would be slower to have to call it on each conversion). Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jun 6 11:12:51 2014
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