While shared variables may be a good idea for memory simulation models, shared variables of protected types are not synthesizable (yet). Arrays used to infer FPGA memory in RTL can either be local variables (not externally accessible for verification), signals (externally accessible, but too much simulation overhead), or old-style, non-compliant shared variables (the reason why most simulators only issue a warning if shared variables are of non-protected types. If most simulators support non-PT shared variables, and their customers are happy to take the responsibility for mutual access, why shouldn't local variables be externally accessible per the standard? Count me as one in favor of restoring non-PT shared variables too, for the same reason as above. Inferred, two-clock FIFOs are a good reason to use them in synthesizable RTL. Simultaneous access to the same array location by two processes has to be avoided for reliable HW anyway, so engineers are used to handling that, and protected types would not help anyway. I love protected types in VHDL, but sometimes they are overkill, and the application does not need that level of protection. Andy D Jones Electrical Engineering Lockheed Martin Missiles and Fire Control Dallas TX -----Original Message----- From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis Sent: Friday, June 06, 2014 12:53 PM To: vhdl-200x@eda.org Subject: EXTERNAL: Re: [vhdl-200x] External variable name Hi Brent, > For external variable names, we can only reference shared variables. > > Apart from the issues of mutual exclusion for accesses, does anyone know of any other reasons why we shouldn't allow references to standard variables within processes? > > When using external names for grey box access in a verification environment, the one thing that is still inaccessible are memory arrays coded as standard variables. > > Can we add this in as a requirement with the proviso that the user is responsible for controlling mutual accesses in the same way as shared variables had to be used pre VHDL2002? Perhaps this is a reason to code your memory arrays as a shared variable. :) Do you have other things that you would like to access. One of the next release candidates for some of the open source work I am doing (OSVVM.org), is our protected type based package for memory models. Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jun 6 16:43:15 2014
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