[vhdl-200x] External variable name

For external variable names, we can only reference shared variables.

Apart from the issues of mutual exclusion for accesses, does anyone know of any 
other reasons why we shouldn't allow references to standard variables within 
processes?

When using external names for grey box access in a verification environment, the 
one thing that is still inaccessible are memory arrays coded as standard variables.

Can we add this in as a requirement with the proviso that the user is 
responsible for controlling mutual accesses in the same way as shared variables 
had to be used pre VHDL2002?


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Regards,

         Brent Hayhoe.

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