Re: [vhdl-200x] Records with diectional subtypes

>>> On 22 August 2012 at 20:11, Brent Hayhoe <Brent.Hayhoe@Aftonroy.com> wrote:
> --Slave entity
> use work.cpu_bus_pkg.all
> entity slave is
....
> bus : comp ( --hierarchical composite port
> adr, dat, we, en(id) : in;
> sdt, ack, err : out;
> en(others) : null
> ) t_cpu_bus
> );

I then have to repeat that on all my slaves. The subtype idea means that the entity doesn't have to know anything about the contents of the "bus" in order to have a pin for it (which is as it should be IMHO).

I'm with Ryan on the "extracting a single bit" functionality. Is there a real-world use-case where this is useful? As far as I know, Avalon, AXI and Wishbone have their masters connected to their slaves through a block of interconnect logic which means that only a single 'en' signal makes it through to the slave anyway. Are there other on-chip buses extant which could make use of this kind of "bus-ripping" feature?

Cheers,
Martin

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Martin Thompson CEng MIET
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