Re: [vhdl-200x] Records with diectional subtypes

Hi Brent,
I see a record as an abstraction that hides details and limits
the number of places where these details need to be known.
Your example enumerates a very simple case where the record
does not descend through any block to a subblock. So in your
example, perhaps it is reasonable to expect the design interface
to know about the elements of the record.

However, if in entity master or slave, there is a subblock that
actually handled all of the interactions with the t_cpu_bus typed
object and then perhaps it is not reasonable to expect master and
slave to know about the elements of t_cpu_bus. Basically at that
point, I might as well have use single element ports.

Best,
Jim

P.S.
Bus is a reserved word (part of guarded signals/blocks), so I
changed your usage of it to cbus below.

> Once more into the breach then.
>
> This time I can't resist re-doing this example with hierarchical
> composite types on the entity ports rather than in the subtypes.
>
> IMHO its more VHDL'ish, slightly less verbose and shouldn't have
> any of the type related problems.
>
>
> package cpu_bus_pkg is
> type t_cpu_bus is record
> adr : std_logic_vector(15 downto 0); --Address
> dat : std_logic_vector(15 downto 0); --Data from master to slave
> we : std_logic; --Write enable from master
> en : std_logic_vector(7 downto 0); --Enable from master
> sdt : std_logic_vector(15 downto 0); --Data from slave to master
> ack : std_logic; --Acknowledge from slave
> err : std_logic; --Error from slave
> end record;
> end package cpu_bus_pkg;
>
> --Master entity
> use work.cpu_bus_pkg.all
> entity master is
> port (
> clk : in std_logic;
> cbus : comp ( --hierarchical composite port
> adr, dat, we, en : out;
> sdt, ack, err : in
> ) t_cpu_bus
> );
> end entity master;
>
> --Slave entity
> use work.cpu_bus_pkg.all
> entity slave is
> generic (
> id : t_id
> );
> port (
> clk : in std_logic;
> cbus : comp ( --hierarchical composite port
> adr, dat, we, en(id) : in;
> sdt, ack, err : out;
> en(others) : null
> ) t_cpu_bus
> );
>
> --Top level
> use work.cpu_bus_pkg.all
>
> signal cpu_bus : t_cpu_bus;
>
> i_master : master
> port map (
> clk => clk,
> cbus => cpu_bus
> );
>
> i_slave_id : slave
> generic map (
> id => 4 --internally 'cbus.en(id)' is the only enable port that exists
> )
> port map (
> clk => clk,
> cbus => cpu_bus --and is mapped to cpu_bus.en(4)
> );
>

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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