Re: [vhdl-200x] Records with diectional subtypes

Once more into the breach then.

This time I can't resist re-doing this example with hierarchical
composite types on the entity ports rather than in the subtypes.

IMHO its more VHDL'ish, slightly less verbose and shouldn't have
any of the type related problems.

package cpu_bus_pkg is
   type t_cpu_bus is record
     adr : std_logic_vector(15 downto 0); --Address
     dat : std_logic_vector(15 downto 0); --Data from master to slave
     we : std_logic; --Write enable from master
     en : std_logic_vector(7 downto 0); --Enable from master
     sdt : std_logic_vector(15 downto 0); --Data from slave to master
     ack : std_logic; --Acknowledge from slave
     err : std_logic; --Error from slave
   end record;
end package cpu_bus_pkg;

--Master entity
use work.cpu_bus_pkg.all
entity master is
   port (
     clk : in std_logic;
     bus : comp ( --hierarchical composite port
               adr, dat, we, en : out;
               sdt, ack, err : in
             ) t_cpu_bus
   );
end entity master;

--Slave entity
use work.cpu_bus_pkg.all
entity slave is
   generic (
     id : t_id
   );
   port (
     clk : in std_logic;
     bus : comp ( --hierarchical composite port
               adr, dat, we, en(id) : in;
               sdt, ack, err : out;
               en(others) : null
             ) t_cpu_bus
   );

--Top level
use work.cpu_bus_pkg.all

   signal cpu_bus : t_cpu_bus;

   i_master : master
     port map (
       clk => clk,
       bus => cpu_bus
     );

   i_slave_id : slave
     generic map (
       id => 4 --internally 'bus.en(id)' is the only enable port that exists
     )
     port map (
       clk => clk,
       bus => cpu_bus --and is mapped to cpu_bus.en(4)
     );

-- 
Regards,
         Brent Hayhoe.
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