RE: [vhdl-200x] Records with diectional subtypes

I agree that drivers must be determined statically. So one could make port subtypes a special case and resolve them statically. An alternative is to define a new category of type, with new rules for port maps.

If you regard a subtype as a restriction on a type, restricting the direction can be seen as keeping to the spirit of VHDL.

Regards,

Peter Flake

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of john.aynsley@doulos.com
Sent: 22 August 2012 12:10
To: vhdl-200x@eda.org
Cc: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Records with diectional subtypes

Don't you have an issue with the concepts of type vs subtype and the determination of drivers? Types get resolved statically, subtypes are not (in general) determined until run-time. Is it not the case that pushing mode info into the subtype makes it too late to determine the drivers of the signals? How is this supposed to be implemented (in the tool)?

Apart from that, the notion of pushing modes into subtypes seems to contradict the conceptual framework of VHDL. But perhaps that's just me being unimaginative ;-)

Cheers,

John A

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