RE: [vhdl-200x] Requirements to do verification

From: <>
Date: Wed Apr 27 2011 - 02:41:14 PDT

Hans, JK,

I love VHDL too. The question I am trying to answer is how we can best
serve the interests of the VHDL community going forward and keep VHDL
relevant. When all the dust has settled on the "marketing statistics"
thing, the point will still stand that VHDL is not the centre of gravity
for constrained random verification at this point in time (just an
opinion). I assert that adding major new features to VHDL for CRV , which
in my humble personal opinion are unlikely to get implemented in a timely
fashion, is not the best use of our effort right now. In my opinion, we
should focus on interoperability with SV and UVM.


John A

27/04/2011 07:01
RE: [vhdl-200x] Requirements to do verification
Sent by:

Let?s stick to this please?
I am not interested in the US/Europe/Asia verification market/statistics
blah blah blah. I subscribed to this mailing list to understand the new
trends and proposed improvements to the language I love most ? VHDL.

From: [] On Behalf 
Of hans@ht-lab
Sent: Tuesday, April 26, 2011 9:28 PM
Subject: Re: [vhdl-200x] Requirements to do verification
Can I also suggest we stop mentioning direct or indirectly the demise of 
VHDL, I really don?t understand what the point is of this. We are a group 
that likes to promote and enhance VHDL any way possible, right?
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Received on Wed Apr 27 02:42:10 2011

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