Re: [vhdl-200x] Requirements to do verification

From: Daniel Kho <daniel.kho@gmail.com>
Date: Wed Apr 27 2011 - 02:59:28 PDT

Hi John,
Constrained random verification is already possible with VHDL, though it is
not yet standardised as part of the standard. Probably we can come to a
consensus on which technique is best to package and ship as the next
revision of the VHDL standard.

From Jim's website, he has a neat way of using protected types together with
impure functions and procedures for constrained random verification. I think
it's worth for the group to invest some of our time (just my opinion) to
have a good look at his methods, review it, and open up discussions on this.

There may be others who have achieved the same thing with different methods.
I think it will be great if you could share with the group your methods for
constrained randomisation. We could then discuss and agree on which solution
is best to be standardised. It could even be a hybrid solution using
different approaches from different people.

That said, I think it wouldn't be too difficult for tool vendors to
implement VHDL-style constrained randomisation, if all they have to do is
include a new VHDL package (or a set of packages/sources) into their
library.

Regards,
Daniel

On Wed, Apr 27, 2011 at 5:41 PM, <john.aynsley@doulos.com> wrote:

> Hans, JK,
>
> I love VHDL too. The question I am trying to answer is how we can best
> serve the interests of the VHDL community going forward and keep VHDL
> relevant. When all the dust has settled on the "marketing statistics" thing,
> the point will still stand that VHDL is not the centre of gravity for
> constrained random verification at this point in time (just an opinion). I
> assert that adding major new features to VHDL for CRV , which in my humble
> personal opinion are unlikely to get implemented in a timely fashion, is not
> the best use of our effort right now. In my opinion, we should focus on
> interoperability with SV and UVM.
>
> Cheers,
>
> John A
>
>
> From: <krishna.janumanchi@wipro.com> To: <vhdl-200x@eda.org> Date: 27/04/2011
> 07:01 Subject: RE: [vhdl-200x] Requirements to do verification Sent by:
> owner-vhdl-200x@eda.org
> ------------------------------
>
>
>
> Letís stick to this please?
> I am not interested in the US/Europe/Asia verification market/statistics
> blah blah blah. I subscribed to this mailing list to understand the new
> trends and proposed improvements to the language I love most Ė VHDL.
>
> --
> Regards,
> JK
>
> *From:* owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org<owner-vhdl-200x@eda.org>]
> *On Behalf Of *hans@ht-lab*
> Sent:* Tuesday, April 26, 2011 9:28 PM*
> To:* vhdl-200x@eda.org*
> Subject:* Re: [vhdl-200x] Requirements to do verification
>
> Can I also suggest we stop mentioning direct or indirectly the demise of
> VHDL, I really donít understand what the point is of this. We are a group
> that likes to promote and enhance VHDL any way possible, right?
>
> Regards,
> Hans.
>
>
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Received on Wed, 27 Apr 2011 17:59:28 +0800

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