RE: [vhdl-200x] Requirements to do verification

John A and all,

     As many know I am a true VHDL bigot and very interested in keeping VHDL
a relevant language. VHDL was created as a design language

to both allow design and design exploration of a component/system and to
document it. I have used VHDL on multiple projects and

it does both exceedingly well. Yes it is verbose and requires more key
stokes to enter versus other languages, but that also is a strength.

    I did years of work on a few projects that used Prolog and Lisp -
logical languages. Those were the best languages for the task at hand.

No single language can do everything.

    Adding features to VHDL that add verification functionality makes a lot
of sense, but competing head to head in the CRV arena means

that the VHDL implementation would have to do it better. I teach my
students - "Use the language most appropriate for the task at

hand." SV does CRV already so providing the ability to interoperate would
be the best way to go (my opinion).

Cheers,

Joanne

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
john.aynsley@doulos.com
Sent: Wednesday, April 27, 2011 5:41 AM
To: vhdl-200x@eda.org
Cc: owner-vhdl-200x@eda.org; vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Requirements to do verification

Hans, JK,

I love VHDL too. The question I am trying to answer is how we can best serve
the interests of the VHDL community going forward and keep VHDL relevant.
When all the dust has settled on the "marketing statistics" thing, the point
will still stand that VHDL is not the centre of gravity for constrained
random verification at this point in time (just an opinion). I assert that
adding major new features to VHDL for CRV , which in my humble personal
opinion are unlikely to get implemented in a timely fashion, is not the best
use of our effort right now. In my opinion, we should focus on
interoperability with SV and UVM.

Cheers,

John A

From:

<krishna.janumanchi@wipro.com>

To:

<vhdl-200x@eda.org>

Date:

27/04/2011 07:01

Subject:

RE: [vhdl-200x] Requirements to do verification

Sent by:

owner-vhdl-200x@eda.org

  _____

Let's stick to this please?
I am not interested in the US/Europe/Asia verification market/statistics
blah blah blah. I subscribed to this mailing list to understand the new
trends and proposed improvements to the language I love most - VHDL.
  

-- 
Regards, 
JK 
  
From: owner-vhdl-200x@eda.org [ <mailto:owner-vhdl-200x@eda.org>
mailto:owner-vhdl-200x@eda.org] On Behalf Of hans@ht-lab
Sent: Tuesday, April 26, 2011 9:28 PM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Requirements to do verification 
  
Can I also suggest we stop mentioning direct or indirectly the demise of
VHDL, I really don't understand what the point is of this. We are a group
that likes to promote and enhance VHDL any way possible, right? 
  
Regards, 
Hans. 
  
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