Re: [vhdl-200x] Requirements to do verification

From: <hans@ht-lab>
Date: Wed Apr 27 2011 - 09:24:46 PDT

Hi John,

I disagree, in my opinion CR is one of the great missing pieces of VHDL (DPI is another one). We have all the power of PSL to do functional verification (bins, etc can be added with some code) but what is missing is support for a proper constraint solver. We are very close, we just need to tie up some loose ends.

I do know that constraint solvers are complex pieces of technology and hence we must adopt whatever is currently supported by SV/SC. The question I have is do we really need OO to get CR support (ala SystemC’ smartpointers) or can we use existing VHDL language constructs like attributes?

What I was thinking about is doing something like:

signal mux_s : std_logic_vector(7 downto 0);
attribute RANDOM : normal; – set distribution
attribute RANDOM of mux_s : std_logic_vector is true;

mux_s’KEEP_OUT(X”55”); -- avoid using illegal value 55
mux_s’KEEP_RANGE(X”33”,X”CC”); -- keep all values from 33 to CC
randomise; -- like a procedure call
mux_s’NEXT; -- get next random value

We do need to add some keywords to call the constraint solver, in this case we should probably VHDL’ existing SV construct:

constraint c1 begin mux_s > X”33” AND mux_s <=X”CC” AND mux_s/=X”55” end;

Another idea, which we discussed a few month ago, is to have better (easier?) support for data introspection. In this case you can bolt on your own constraint solver (perhaps SCV or Minion). We might need some additional simulator hooks like start_of_simulation() and end_of_elaboration() but these are already supported by SV/SC so might not be to complex/expensive to implement.

What I suspect will not work is pages and pages of complex VHPI code, we need something as simple as a DPI call to an external library perhaps called from a user define attribute (e.g. mux_s’myfunc() calls myfunc DPI function with a pointer to mux_s).

Just some thoughts,


Sent: Wednesday, April 27, 2011 10:41 AM
Cc: ;
Subject: RE: [vhdl-200x] Requirements to do verification
Hans, JK,

I love VHDL too. The question I am trying to answer is how we can best serve the interests of the VHDL community going forward and keep VHDL relevant. When all the dust has settled on the "marketing statistics" thing, the point will still stand that VHDL is not the centre of gravity for constrained random verification at this point in time (just an opinion). I assert that adding major new features to VHDL for CRV , which in my humble personal opinion are unlikely to get implemented in a timely fashion, is not the best use of our effort right now. In my opinion, we should focus on interoperability with SV and UVM.


John A

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Received on Wed Apr 27 09:30:21 2011

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