Re: [vhdl-200x] Why OOP vs Generics

From: Jim Lewis <>
Date: Fri Apr 22 2011 - 10:36:44 PDT

Hi Evan,
> My own view now is that the requirements of electronic and verification
> engineers are so widely separated that it just doesn't make sense to try
> to shoehorn everything into one language. ...
> The verification guys have no interest in (1) structural.
> They've also moved on from (2) procedural to OOP/AOP.
> Are they even that interested in (3) highly parallel and (4) time?
> They can get the parallelism they need from threads, rather than
> processes, and I don't think they're even that concerned with time beyond
> getting a look in on every cycle.

My own view is that perhaps the SV approach has gone off the deep end.
It seems that they have ditched structural code (simple concurrent
calls - wheos elaboration and initialization is handled by the language)
and replaced it with an OO approach that requires the user to be use
methods to connect different models together, methods to initialize the
model's data structures, methods to put the model into functional mode, ...
So while at the end of the day, the SV approach re-uses alot of cool stuff,
it is substantially more tedious than VHDL (was this the objective) and it
is simply doing design elaboration and initialization (something that
VHDL does automatically).

Keep in mind that VHDL architectures + configurations pretty much
do the same thing that SV factories do. In addition, if I really need
dynamic elaboration of concurrent items, why not just extend "if generate"
to allow dynamic elaboration?

> In fact, when you're writing verification
> code, once you've done the one-off basic low-level communication with the
> DUT, everything else you do is completely unrelated to the HDL/process/time/
> "electronics"/paradigm -
Didn't you do this also when you did VHDL? Once I write the bus functional
models for my interfaces - which do the low-level communication with the
DUT - I focus on generating the test cases.

> it's all verification plans, functional coverage,
> closure, temporal assertions, directed generation, scoreboarding,
> and so on. Anyone who thinks that VHDL should be retro-fitted with all
> this stuff needs to make a very, very, good case for it.

VHDL-2008 added PSL, so the language already had temporal assertions.

In my current verification approach, I have packages that support
randomization and constrained random test generation (via procedural
code), scoreboarding, memories, fifos, and functional coverage.
The current functional coverage package is a little clunky, but I am
mostly through the next revision of the package and it will have features
that I do not currently see in SystemVerilog or 'e'.

So what I am looking for in the VHDL revision is an improvement
in some key features that make it possible to more effectively
do some of the package based implementations I have already

Do you have a list beyond what is above, so I can understand why
you feel it is not possible to do all of this in VHDL?

Best Regards,

Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Fri Apr 22 10:37:17 2011

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