Re: [vhdl-200x] Why OOP vs Generics

On 22/04/2011 18:36, Jim Lewis wrote:

> Do you have a list beyond what is above, so I can understand why
> you feel it is not possible to do all of this in VHDL?

Well, you asked, so I've attached some notes which are more a stream of
consciousness than a list. A good place to start with a specific list is
the e LRM; the draft is still available on the web, at
www.ieee1647.org/downloads/P1647_Draft_6_071214.pdf.

Chapter 14 covers defining coverage items; see cross-coverage for a
flavour of what's involved. Chapter 9 is the introduction to stimulus
generation. This is complicated, and might take a week or two to get
into for someone who hasn't been exposed to it before.

I think the right way to go about this is to define a small number of
basic verification problems, and to ask for volunteers to code them in e
and SV. This would give you a starting point for defining an equivalent
syntax in VHDL.

BTW, my own view is that it's not desirable, rather than not possible.

-Evan

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