Re: [vhdl-200x] Why OOP vs Generics

Hi Evan,
>> Do you have a list beyond what is above, so I can understand why
>> you feel it is not possible to do all of this in VHDL?
>
> Well, you asked, so I've attached some notes which are more a stream of consciousness than a list. A good place to start with a specific list is the e LRM; the draft is still available on the web, at
> www.ieee1647.org/downloads/P1647_Draft_6_071214.pdf.
>
> Chapter 14 covers defining coverage items; see cross-coverage for a flavour of what's involved.
> Chapter 9 is the introduction to stimulus generation.
> This is complicated, and might take a week or two
> to get into for someone who hasn't been exposed to it before.

Note this chapter has moved around some between versions.
I have a version with it in chapter 12 and a version of it being
in chapter 15 (8.3). In SV, functional coverage is in chapter
18 of P1800/D2, March 16, 2007.

Functional coverage and randomization are on my short list
for VHDL. I am also intimately familiar with these chapters
in 'e' as well as the corresponding chapters in the SystemVerilog.

First some terminology for the group. When we collect cover a
single object 'e' calls this item coverage and SV calls this
a coverage point. Both languages use the term cross coverage
to describe the relationship between multiple objects.

When describing item /point coverage and breaking the
coverage down into separate bins, how limiting is it to only
allow one range per bin vs allowing each individual bin to contain
a set of items or multiple ranges? In theory this seems bad, however,
in practice, it seems likely that I need to see one of each
non-contiguous ranges or set member separately - and hence - perhaps
it makes sense to require them to be placed in separate bins.
Can you or others comment?

When describing cross coverage, is a simple cross of items sufficient,
or do we need some additional help to remove or mark bins that are
either illegal (not permitted to occur) or to be ignored (because they
can never happen)? It seems like marking or removing bins to be
ignored is important, as otherwise, how do we sanely report missing
coverage items?

> I think the right way to go about this is to define a small number
> of basic verification problems, and to ask for volunteers to code
> them in e and SV. This would give you a starting point for defining
> an equivalent syntax in VHDL.

Do you have any suggested problems?

> BTW, my own view is that it's not desirable, rather than not possible.
Unless of course we do something better in a simpler fashion.
For example, if you have Andrew Piziali's book,
_Functional Verification Coverage Measurement and Analysis_
I don't see any cross coverage model that handles the
Hybrid Coverage Model he presents in figure 4.5 in a simple
fashion.

Back to my original question. Lets assume that we solve the
random generation and the functional coverage in a simple
fashion.

What other essential things have we missed?
I have seen some imply that dynamic elaboration is essential.
Is this true or is it a requirement of a certain methodology
and not a requirement for others?

Best,
Jim

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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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