Re: [vhdl-200x] Requirements to do verification

Hi Ben,
"but they felt that OVM is superior to what they had before in the design of
their testbench in VHDL, and thus the total switch."
Yes, I see this trend happening in my place as well, but that's because
there are quite a significant number of US-based design centres in my place,
and probably you're seeing things from the US perspective.

I see yet another trend happening at my place, which is more European
companies setting up their design centres (many new buildings in
construction). That would mean more VHDL jobs in future (and more VHDL
usage). Hopefully, Australia would do the same thing too (I know VHDL is
pretty strong in Australia).

Also, though I know many US companies have switched to SystemVerilog, I have
heard some who would rather stick with VHDL.

Well, there will come a time when companies will just get tired of switching
languages, as HDLs compete with one another and after some time, a lagging
HDL will again lead the market and usage space. This is one of the reasons
why I would rather not re-learn a new language that can do the same thing.
Whatever that could be worked around, I'll live with that first while I wait
for a newer revision of the standard to emerge, and start pushing tool
vendors to support those new features.

I think the same thing happened with Verilog about the 2002~2005 timeframe,
where they probably had almost the same kinds of discussions we are having
now. And they did come up with SystemVerilog 2005, which will lead the
market for some time, but I'm going to wait till VHDL-2008 starts leading
the market again. Well, I see this cycle repeating itself, and I don't see
it as a bad thing, because that means we progress with better and more
usable HDL standards.

Regards,
Daniel Kho

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