Re: [vhdl-200x] Requirements to do verification

Daniel, et al,

There's a difference in language usage for design and usage for verification. Vera and e were used for verification with VHDL before SV existed. Although all designers do some amount of verification, many organizations and projects have dedicated verification teams.

The requirement to use the same language in both areas is loose or minimal. In fact, ask any experienced Verilog designer who moved into verification and they will tell you that using SV for verification is like having to learn a new language. Syntactic familiarity is of minimal help as the mental concepts and thought processes in using dynamic classes and objects, factories (and other UVM objects) have no corollary in static, Verilog RTL design.

In the languages-are-tools category, I will also point out that, from my experience, most people doing TL and ESL design and verification use C/C++ for design and C/C++ or SystemC for verification. Neither 100% in either case. Some use SystemC for design (where users actually write SC code) and there is a company that offers solutions for SV use in TL design. For SoC verification, we see many users writing C code to test integration of blocks and system-level functionality.

What need in the market (target market needs explicit identification too) is VHDL going to address better than anything currently available as a language tool?

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Stephen Bailey

On Apr 26, 2011, at 10:36 AM, "Daniel Kho" <daniel.kho@gmail.com<mailto:daniel.kho@gmail.com>> wrote:

Hi Ben,
"but they felt that OVM is superior to what they had before in the design of their testbench in VHDL, and thus the total switch."
Yes, I see this trend happening in my place as well, but that's because there are quite a significant number of US-based design centres in my place, and probably you're seeing things from the US perspective.

I see yet another trend happening at my place, which is more European companies setting up their design centres (many new buildings in construction). That would mean more VHDL jobs in future (and more VHDL usage). Hopefully, Australia would do the same thing too (I know VHDL is pretty strong in Australia).

Also, though I know many US companies have switched to SystemVerilog, I have heard some who would rather stick with VHDL.

Well, there will come a time when companies will just get tired of switching languages, as HDLs compete with one another and after some time, a lagging HDL will again lead the market and usage space. This is one of the reasons why I would rather not re-learn a new language that can do the same thing. Whatever that could be worked around, I'll live with that first while I wait for a newer revision of the standard to emerge, and start pushing tool vendors to support those new features.

I think the same thing happened with Verilog about the 2002~2005 timeframe, where they probably had almost the same kinds of discussions we are having now. And they did come up with SystemVerilog 2005, which will lead the market for some time, but I'm going to wait till VHDL-2008 starts leading the market again. Well, I see this cycle repeating itself, and I don't see it as a bad thing, because that means we progress with better and more usable HDL standards.

Regards,
Daniel Kho

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