[vhdl-200x] Requirements to do verification

From: Jim Lewis <Jim@synthworks.com>
Date: Fri Apr 22 2011 - 10:04:38 PDT

If we are to make VHDL a viable verification language,
what features do we require?

I am thinking the main ones are functional coverage,
randomization, data structures (ie: scoreboards,
memories, fifos, ...) and interfaces.

While I realize some have expressed concern about a language's
ability to be suited for both design (RTL and above) and
verification, I am not sure I agree. I think a frugal
implementation of all of the above is possible.

The more I work with VHDL the more I am impressed by the


Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
Expert VHDL Training for Hardware Design and Verification
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Received on Fri Apr 22 10:05:13 2011

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