Re: [vhdl-200x] Requirements to do verification

From: Ken Campbell <>
Date: Fri Apr 22 2011 - 11:36:53 PDT

Hello everyone,
As an answer to the question.
I think the additions to VHDL should enable the implementation of a “look
and feel” of UVM. Initially the target should be the objects that provide
the most value to a verification environment. Like some kind of subset of
UVM that would enable the most important verification tasks to be
automated, basic building blocks and interfacing...

The reason I say this is because there is a wave of SV usage. I currently
can not get employed because I do not have experience with any SV methods,
but have been doing verification for 15 years now. I got left behind
using a VHDL test bench system I published on OpenCores. Now after 3
months, at least 10 ASIC/FPGA verification jobs have gone by because of my
lack of specific verification tool methods / language.

So, to improve the chances of cross employment and standardization for the
future of verification people, I recommend a UVM methods implementation as
a target for VHDL language enhancements.

As Jim said, VHDL is very capable and very much alive. I have recently
started a blog describing how to best use the VHDL test bench package I
published. This has increased the downloads from 1-3 per day to 4-7. The
blog is getting more attention than I thought it would and for me that is
evidence that VHDL is very much alive.

Is this the kind of input you were looking for?

Ken Campbell

> All,
> If we are to make VHDL a viable verification language,
> what features do we require?
> I am thinking the main ones are functional coverage,
> randomization, data structures (ie: scoreboards,
> memories, fifos, ...) and interfaces.
> While I realize some have expressed concern about a language's
> ability to be suited for both design (RTL and above) and
> verification, I am not sure I agree. I think a frugal
> implementation of all of the above is possible.
> The more I work with VHDL the more I am impressed by the
> capability.
> Best,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training
> SynthWorks Design Inc.
> 1-503-590-4787
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.

This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Fri Apr 22 11:37:13 2011

This archive was generated by hypermail 2.1.8 : Fri Apr 22 2011 - 11:37:27 PDT