Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

From: ben cohen <>
Date: Mon Mar 07 2011 - 16:58:05 PST

In SystemVerilog, an interface is a declaration that encapsulates the
connectivity between two or more design units.
In VHDL you have the entity declaration and the architecture declaration.
 In SystemVerilog. an interface is instantiated ust like a module
instantiation. It is then connected to the appropriate module of class

An interface allows a number of signals to be grouped together and be
represented as a single port. An interface can have port a list. For
interface fifo_if(input wire clk,
                  input wire reset_n);

An interface can also have modports. A modport declaration is specified in
an interface declaration to define the directions of signals used in the
application (e.g., output for the driver of the *data*, and input for the
receiver of the *data *).
The following link provides a complete example of how an interface s used in
a VMM application. (BTW, I have the rights to
this book, thus permission is hereby given to freely access and use this
material as needed). The interface model is:
*interface* fifo_if(input wire clk,
                  input wire reset_n);
   timeunit 1ns; timeprecision 100ps;
  import fifo_pkg::*;
  wire push; // push data into the fifo
  wire pop; // pop data from the fifo
  wire full; // fifo is at maximum level
  wire empty; // fifo is at the zero level (no data)
  wire almost_empty, almost_full;

  wire error; // fifo push or pop error
  // word_t data_in;
  wire [WIDTH-1:0] data_in;
  wire [WIDTH-1:0] data_out;

  parameter hold_time=3; // 3ns
  parameter setup_time = 5;

  clocking slave_cb @ (posedge clk);
 // default input #5ns output #hold_time;
// output empty, full, data_out, error;
// input data_in, push, pop;
  endclocking : slave_cb

  *clocking driver_cb @ (posedge clk);*
* default input #setup_time output #hold_time;*
* input empty, full, data_out, error;*
* output data_in, push, pop;*
* endclocking : driver_cb*

  *modport *fslave_if_mp (// clocking slave_cb, // 11/05/06
                        output empty,
                        output full,
                        output data_out,
                        output error,
output almost_empty,
 output almost_full,
                        input data_in,
                        input push,
                        input pop);
  // input clk);

  // FIFO driver
   *modport *fdrvr_if_mp (clocking driver_cb);

// FIFO Monitor if.
 *clocking mon_cb @ (posedge clk);*
* default input #setup_time output #hold_time;*
* input empty, full, data_out, error;*
* input data_in, push, pop;*
* endclocking : mon_cb*

  modport fifo_mon_if_mp (clocking mon_cb);

endinterface : fifo_if

shown in the above example is the fact that *assertions are also allowed
within an interface*.
Assertions can also be bound to an interface.
An interface declaration needs to be instantiated to be used.

In the top level testbench, the interface is instantiated:
module fifo_tb;
  logic clk = 1'b0; // system clock
  logic reset_n;

  *fifo_if f_if(.*); // instantiation of fifo interface*
 * fifo_csr_if f_csr_if_0 (.*);*

  fifo_test_pgm utest_pgm ();
 * fifo fifo_rtl_1(.f_csr_if(f_csr_if_0), .*); // instantiation of fifo DUV*
  bind fifo fifo_props fifo_props_1(.*, .fifo_if(f_if)); // for assertions
defined externally
endmodule : fifo_tb

 In the environment class:
*class Fifo_env extends vmm_env;*
 this.fifo_cmd_xactor_0 = new("cmd_xactor",
* * * `TOP.f_if, *

The RTL unit uses the slave modport. Here is an example:
module fifo (input clk, input reset_n, *fifo_if.fslave_if_mp f_if*,
// fifo_csr_if.fifo_ctl_mp f_csr_if
     fifo_csr_if.fifo_ctl_mp f_csr_if
 always @*
      if (!f_if.push && *!f_if.pop*) push_pop = NONE;
      else if ( f_if.push && !f_if.pop) push_pop = PUSH;
      else if (!f_if.push && f_if.pop) push_pop =POP;
      else if ( f_if.push && f_if.pop) push_pop = PSPP;

  assign f_if.data_out=data_out_reg;
  assign f_if.error = error_reg;
I think that interfaces a la SystemVerilog are very powerful, as they
provide a greater use model because
1) An interface declaration allows for the definition of modports to
identify directions in which it is used.
2) It collapses all the related objects in one declaration (like a record
3) It allows assertions to be declared within the declaration or bound to

It would be good if this group considers the interface declaration. Keep in
mind that they are used in the world of VMM /OVM /UVM, even if the RTL unit
does not use the interface.
Ben Cohen

On Mon, Mar 7, 2011 at 2:44 PM, Jones, Andy D <> wrote:

> By what means is an interface invoked in SV, inheritance? We have no
> inheritance mechanism in VHDL, but I’m open to adopting as much of an SV
> implementation as is practical in VHDL.
> In essence, a “named composite mode” (I’m not exactly sure what to call
> what I want) would be an “interface” of sorts. My notion (probably
> incorrect) of an interface is that of an endpoint on a conduit. The record
> defines the data content of the conduit, and the composite mode defines the
> endpoint.
> On a slightly different note, the ability to define an assertion on a type
> or subtype (or composite mode) in VHDL could come in very handy.
> *Andy D Jones
> *Electrical Engineering
> Lockheed Martin Missiles and Fire Control
> Dallas TX
> Cell: 817-422-3124
> *From:* ben cohen []
> *Sent:* Monday, March 07, 2011 9:01 AM
> *To:*
> *Cc:* Jones, Andy D
> *Subject:* Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list
> SystemVerilog has the interface declaration that allows directions
> definitions with modports. An interface declaration also allows the us of
> assertions used in that interface, thus applying the assertions for every
> instance of that interface.
> Why is the idea of an interface declaration ignored?
> Ben Cohen
> On Mon, Mar 7, 2011 at 6:43 AM, Jones, Andy D <>
> wrote:
> You can use records on inout ports, but every element of the record must be
> inout, which then effectively restricts the usage to resolved types on all
> elements of the record, and the explicit specification of benign drivers on
> elements which are only used as inputs.
> I am in favor of a m echanism to allow different modes on different
> elements of a record port, while mapping the entire record to the
> (composite) port in one association. Whether that should be a named
> composite mode for the record type or some other means is open to
> suggestions.
> Andy D Jones
> Electrical Engineering
> Lockheed Martin Missiles and Fire Control
> Dallas TX
> -----Original Message-----
> From: [] On Behalf
> Of David Koontz
> Sent: Friday, March 04, 2011 1:43 AM
> To:
> Subject: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list
> On 1/03/11 10:41 PM, Martin.J Thompson wrote:
> > * Using records on inout pins in some fashion (or is that doable in
> > 2008 and I haven't found out how yet?)
> We could consider that a port is a structure (record) and is accessed
> (connected) through a portmap.
> Are you after other ways to make connectivity such as inferred signals
> (wires)?
> > * Easy efficient external language interface (to Python - ideally I'd
> > like to write my whole testbench in Python).
> I don't seem to recall that Python is either an ANSI or IEEE standard. This
> sounds like a case of 'who bells the cat' and does VHPI for Python, as well
> as issues on operating an elaborated model which are outside of the current
> scope of the standard. You could get the idea this is a tool domain issue.
> --
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Received on Mon Mar 7 16:58:59 2011

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