Re: [vhdl-200x] VHDL enhancements wish list

On 19/02/2011 00:52, ben cohen wrote:

> From P1800'2009
> *9.2.2.2 Combinational logic always_comb procedure*
> SystemVerilog provides a special always_comb procedure for modeling
> combinational logic behavior. For example:
> always_comb
> a = b & c;
> always_comb
> d <= #1ns b & c;
> The always_comb procedure provides functionality that is different from
> the general purpose always procedure:
> — There is an inferred sensitivity list that includes the expressions
> defined in 9.2.2.2.1.
> — The variables written on the left-hand side of assignments shall not
> be written to by any other process. However, multiple assignments made
> to independent elements of a variable are allowed as long as their
> longest static prefixes do not overlap (see 11.5.3). For example, an
> unpacked structure or array can have one bit assigned by an always_comb
> procedure and another bit assigned continuously or by another
> always_comb procedure, etc. See 6.5 for more details.
> — The procedure is automatically triggered once at time zero, after all
> initial and always procedures have been started so that the outputs of
> the procedure are consistent with the inputs. Software tools should
> perform additional checks to warn if the behavior within an always_comb
> procedure does not represent combinational logic, such as if latched
> behavior can be inferred.

SV added 'always_comb' only because the modelling of combinatorial logic
was broken in Verilog, and had been for 20 years. Specifically, the
problem is described in the last item of the list above (which describes
how signal initialisation is broken in Verilog).

VHDL never had these problems, by design. To start adding this sort of
syntax (or the other 'enhancements' from the other threads) would be, to
put it mildly, a retrograde step.

Might I suggest, respectfully or otherwise, that some of the discussion
on this list might be better carried out on comp.lang.vhdl or
comp.lang.verilog.

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