Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

On 8/03/11 11:27 AM, Jones, Andy D wrote:
> I would use the same record type definition, with one or more named
> composite modes defined for that record type (e.g. "master" & "slave").
>
> But I'm certainly open to other ideas.

Modes are associated with ports. You need a unique mode map for every
component. Some components can drive particular signals which others may
not while using them as inputs. An example would a bus interconnected to
several components.

It would seem you could map a record onto a port with formal association of
an existing port declaration through a port map and an additional layer of
hierarchy. This doesn't present any work savings, when the mode is
required for declaration of drivers and semantic limitation testing.

While not alleviating the work involved in the port interface declaration to
map modes you could have a mechanism to map a record onto formals in a port
map as simply as possible. A problem with that is port mapping is done by
associating formals with external signals and not the other way around. At
the least it might require a formal of NULL as a space holder of things not
used from the record:

port map (

 SYSBUS'(
        ADDR, -- mode in
        DATA, -- mode inout
        R_W, -- mode in
        READ_EN_N, -- mode in
        INTA_N, -- mode out
        NULL, -- sysbus record has an INT B not used in component
        IRQ_N, -- mode inout
        IACK_N -- mode in
  ) => SYSBUS

A little more savings could be had by declaring the record compatibility in
the port declaration:

port (
  record SYSBUS is
        ADDR: in std_logic_vector(17 downto 0);
        DATA: inout std_logic_vector(7 downto 0);
        R_W: in std_logic;
        READ_EN_N: in std_logic;
        INTA_N: out std_logic;
        NULL: ;
        IRQ_N: inout std_logic;
        IACK_N: in std_logic;
  end record [SYSBUS];
)

with

 portmap (SYSBUS => SYSBUS) -- in a component instantiation

Two address methods, e.g. SYSBUS.ADDR and ADDR, The later sounds easier to
deal with inside a component. The former for continuity at the abstraction
level. You could use either one in a binding indication but not both for
the same element. (Using formal SYSBUS would preclude using ADDR, although
you can imagine cases where it would be nice to bind to port/record elements
with an aggregate, even an element binding overload).

Note that because the modes have to be declared you can't not list the
elements somewhere. You'd be able to declare more than one record in port
or port map binding indication.

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