RE: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

By what means is an interface invoked in SV, inheritance? We have no inheritance mechanism in VHDL, but I'm open to adopting as much of an SV implementation as is practical in VHDL.

In essence, a "named composite mode" (I'm not exactly sure what to call what I want) would be an "interface" of sorts. My notion (probably incorrect) of an interface is that of an endpoint on a conduit. The record defines the data content of the conduit, and the composite mode defines the endpoint.

On a slightly different note, the ability to define an assertion on a type or subtype (or composite mode) in VHDL could come in very handy.

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control
Dallas TX
Cell: 817-422-3124

From: ben cohen [mailto:hdlcohen@gmail.com]
Sent: Monday, March 07, 2011 9:01 AM
To: vhdl-200x@eda.org
Cc: Jones, Andy D
Subject: Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

SystemVerilog has the interface declaration that allows directions definitions with modports. An interface declaration also allows the us of assertions used in that interface, thus applying the assertions for every instance of that interface.

Why is the idea of an interface declaration ignored?
Ben Cohen systemverilog.us<http://systemverilog.us>
On Mon, Mar 7, 2011 at 6:43 AM, Jones, Andy D <andy.d.jones@lmco.com<mailto:andy.d.jones@lmco.com>> wrote:
You can use records on inout ports, but every element of the record must be inout, which then effectively restricts the usage to resolved types on all elements of the record, and the explicit specification of benign drivers on elements which are only used as inputs.

I am in favor of a mechanism to allow different modes on different elements of a record port, while mapping the entire record to the (composite) port in one association. Whether that should be a named composite mode for the record type or some other means is open to suggestions.

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control
Dallas TX
-----Original Message-----
From: owner-vhdl-200x@eda.org<mailto:owner-vhdl-200x@eda.org> [mailto:owner-vhdl-200x@eda.org<mailto:owner-vhdl-200x@eda.org>] On Behalf Of David Koontz
Sent: Friday, March 04, 2011 1:43 AM
To: vhdl-200x@eda.org<mailto:vhdl-200x@eda.org>
Subject: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

On 1/03/11 10:41 PM, Martin.J Thompson wrote:
> * Using records on inout pins in some fashion (or is that doable in
> 2008 and I haven't found out how yet?)

We could consider that a port is a structure (record) and is accessed
(connected) through a portmap.

Are you after other ways to make connectivity such as inferred signals
(wires)?

> * Easy efficient external language interface (to Python - ideally I'd
> like to write my whole testbench in Python).

I don't seem to recall that Python is either an ANSI or IEEE standard. This
sounds like a case of 'who bells the cat' and does VHPI for Python, as well
as issues on operating an elaborated model which are outside of the current
scope of the standard. You could get the idea this is a tool domain issue.

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