Re: [vhdl-200x] Request for Input

On 1/3/2011 9:50 AM, Daniel Kho wrote:

> Also, using a z-transform function to represent a clocked delay stage is
> a really cool idea (it really means what it says).
>
> /Maybe a attribute to set a default clock, reset and enable? Then it
> would look like:
>
> Z'default_clock := clk;
> Z'default_reset := rst;
> Z'default_enable := '1';
>
> Z : zt (x**2 / y, 15);
>
> /Here I'm assuming 15 z-transform delay stages are used (since we can't
> have time units in nanoseconds with are not synthesizable)? So, does
> this mean that it takes 15 clock cycles to implement this logic?

Yes. It would have to function the same way a bank of registers does.
There would also have to be a:
Z'reset_value := (others => '0');
Assumed as a default.

The interface to the function would look like:
function zt (arg : <sometype>;
clock : std_ulogic := arg'default_clock;
reset : std_ulogic := arg'default_reset;
enable : std_ulogic := arg'default_enable;
reset_value : <sometype> := arg'default_reset_value)
return <sometype>;

> // > Maybe a built in operator?
>>
>> Z <= x**2/y @ 15;
>
> Well, maybe. Which clock, though?
>
> Yes, brilliant. Or even, following the name of your z-transform function:
> Z <= x**2/y zt 15;
>
> Jonathan,
> The clock is passed directly to the "zt" function. And I'm assuming that
> the attributes perform the mapping between the design's clock, reset,
> and enable signals to this function. So, I think what David is saying is
> this:
>
> Top-level design:
>
> --Maps top-level clocks, reset, and enable signals to the function.
> Similar to port-mapping.
> --Here, the "Z" signal needs to be checked (by the compiler) to use the
> "zt" function, as in the expression above.
> /Z'clock := clk;
> Z'reset := rst;
> Z'enable := '1';/

Yes.

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