RE: [vhdl-200x] Request for Input

Hi Jim,

I have an interested bystander's view of the VHDL enhancement process, since
I am from a Verilog/Superlog/SystemVerilog background. Part of the
motivation for Superlog and SystemVerilog was to catch up with VHDL features
such as data structures and automatic variables. SystemVerilog is such a
large language that four sub-committees are needed to consider enhancements:
basic language, testbench, assertions and C interface.

In the case of VHDL the language is already large. One could consider that
e and PSL fulfil the roles of testbench and assertions, and they have their
own committees. So a direct C interface is probably the area that needs
attention. This should make it easier to inter-operate with other
languages, including SystemC and SystemVerilog as you suggest, in a standard
way.

Regards,

Peter.

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Jim Lewis
Sent: 18 December 2010 09:23
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Request for Input

Hi,
During the last meeting Victor Berman requested that the study group provide
a report to accompany the PAR that further elaborates on the purpose of the
PAR:

  "The VHDL language was defined for use in the
   design and documentation of electronics systems. It is being
   revised to incorporate capabilities that improve the language's
   usefulness for its intended purpose as well as extend it to address
   design verification methodologies that have developed in industry.
   These new design and verification capabilities are required to
   ensure VHDL remains relevant and valuable for use in electronic
   systems design and verification."

In reality, the PAR is this general since the working group will vote on and
decide exactly what this means, however, since it is likely that I will
asked to answer this during the DASC meeting it would be nice to have ideas
from the study group.

For example, what is intended by verification enhancements?
This could mean something like:
Create an API/interface/package that allows interfacing VHDL to SystemC
and/or SystemVerilog/UVM.

It could also mean we implement full OO and UVM-like stuff in VHDL.

What I present to DASC may end up being a range of ideas that the working
group will have to decide on.

With that, let the discussion begin.

I hope to present this at the January 6 DASC meeting.

Best,
Jim

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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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