[vhdl-200x] Request for Input

Hi,
During the last meeting Victor Berman requested that
the study group provide a report to accompany the PAR
that further elaborates on the purpose of the PAR:

  "The VHDL language was defined for use in the
   design and documentation of electronics systems. It is being
   revised to incorporate capabilities that improve the language's
   usefulness for its intended purpose as well as extend it to address
   design verification methodologies that have developed in industry.
   These new design and verification capabilities are required to
   ensure VHDL remains relevant and valuable for use in electronic
   systems design and verification."

In reality, the PAR is this general since the working group
will vote on and decide exactly what this means, however,
since it is likely that I will asked to answer this during
the DASC meeting it would be nice to have ideas from the
study group.

For example, what is intended by verification enhancements?
This could mean something like:
Create an API/interface/package that allows interfacing
VHDL to SystemC and/or SystemVerilog/UVM.

It could also mean we implement full OO and UVM-like
stuff in VHDL.

What I present to DASC may end up being a range of
ideas that the working group will have to decide on.

With that, let the discussion begin.

I hope to present this at the January 6 DASC meeting.

Best,
Jim

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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