Re: [vhdl-200x] Request for Input

Jim,
Ideally, it would be great if VHDL can implement full OO for use of
frameworks like UVM.
However, in order for that to be successful, I believe that a full
implementation a la SystemVerilog would be needed so that all the libraries
already implemented in VMM/OVM/UVM could be reused with a simple program
translator. Partial implementation is troublesome, as it would be
expensive to manually translate those libraries.
Also, attempting to implement in VHDL the full OO a la SystemVerilog is
troublesome because we would be talking about differences in syntax and the
implementation of zones where objects are updated. That VHDL implementation
would be lagging far behind all the years where SystemVerilog made a lot of
ground in that field.

I strongly believe that a better approach would be to create an
API/interface/package that allows interfacing VHDL to SystemC and/or
SystemVerilog/UVM.
Currently the SystemVerilog LRM has no mention of VHDL; however, tool
vendors have adopted conventions to allow mixed level simulations. I would
like to see something more formal in integrating VHDL and SystemVerilog.

 --------------------------------------------------------------------------
Ben Cohen (831) 345-1759
http://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN
878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004,
ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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On Sat, Dec 18, 2010 at 1:23 AM, Jim Lewis <Jim@synthworks.com> wrote:

> Hi,
> During the last meeting Victor Berman requested that
> the study group provide a report to accompany the PAR
> that further elaborates on the purpose of the PAR:
>
> "The VHDL language was defined for use in the
> design and documentation of electronics systems. It is being
> revised to incorporate capabilities that improve the language's
> usefulness for its intended purpose as well as extend it to address
> design verification methodologies that have developed in industry.
> These new design and verification capabilities are required to
> ensure VHDL remains relevant and valuable for use in electronic
> systems design and verification."
>
> In reality, the PAR is this general since the working group
> will vote on and decide exactly what this means, however,
> since it is likely that I will asked to answer this during
> the DASC meeting it would be nice to have ideas from the
> study group.
>
> For example, what is intended by verification enhancements?
> This could mean something like:
> Create an API/interface/package that allows interfacing
> VHDL to SystemC and/or SystemVerilog/UVM.
>
> It could also mean we implement full OO and UVM-like
> stuff in VHDL.
>
> What I present to DASC may end up being a range of
> ideas that the working group will have to decide on.
>
>
> With that, let the discussion begin.
>
> I hope to present this at the January 6 DASC meeting.
>
> Best,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
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