Re: [vhdl-200x] Request for Input

Hi David and all,
*I think that something like:
function zt ( var : <some type>
clock: std_ulogic;
reset: std_ulogic;
delay: Positive := 1;
enable: std_ulogic : ='1')
return <some type>;
might work. Might be something to play with.

The hope would be to let the synthesis tool figure out the divider style
(given some constraints) and move the FFs back into the divider until timing
is met.
*
Even better. With this, we could directly use functions and allow them to be
clocked. My earlier suggestion of using functions to access processes is an
indirect way to clock a function, and a workaround to this direct approach.
If implementing this approach is possible in the standard, this would be
even better than my earlier suggestion (of having that workaround).

Also, using a z-transform function to represent a clocked delay stage is a
really cool idea (it really means what it says).

*Maybe a attribute to set a default clock, reset and enable? Then it would
look like:

Z'default_clock := clk;
Z'default_reset := rst;
Z'default_enable := '1';

Z : zt (x**2 / y, 15);

*Here I'm assuming 15 z-transform delay stages are used (since we can't have
time units in nanoseconds with are not synthesizable)? So, does this mean
that it takes 15 clock cycles to implement this logic?

** > Maybe a built in operator?
>
> Z <= x**2/y @ 15;

Well, maybe. Which clock, though?

Yes, brilliant. Or even, following the name of your z-transform function:
Z <= x**2/y zt 15;

Jonathan,
The clock is passed directly to the "zt" function. And I'm assuming that the
attributes perform the mapping between the design's clock, reset, and enable
signals to this function. So, I think what David is saying is this:

Top-level design:

--Maps top-level clocks, reset, and enable signals to the function. Similar
to port-mapping.
--Here, the "Z" signal needs to be checked (by the compiler) to use the "zt"
function, as in the expression above.
* Z'clock := clk;
Z'reset := rst;
Z'enable := '1';*

Package or separate VHDL file:
*function zt ( var : <some type>
clock: std_ulogic;
reset: std_ulogic;
delay: Positive := 1;
enable: std_ulogic : ='1')
return <some type>;*

Nice discussion, hope everyone enjoyed Christmas and the New Year!

Regards,
Daniel Kho

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