RE: [vhdl-200x] Request for Input

What about using generate statements in VHDL to control which processes you want to be synthesized? I have my own personal DSP library that makes extensive use of this and have begun implementing VHDL entities that are very identical to the Mathworks Simulink DSP and Communication blocksets ( I now have less of a reason to use their tools). I have attached a numerically controlled oscillator with an IQ ROM component that shows a fully parameterizable complex numerically controlled oscillator using generate statements. The NCO is completely synthesizable. I have targeted Altera boards with it. This code illustrates how to use a VHDL shorthand for a delay that is a multiple of the clock rate using a clocked process. This shorthand is synthesizable and exploits the VHDL type system. I have attached a unitdelay_eac.vhd and a varunitdealy_eac.vhd that illustrate this outside of the NCO example. The unit delay and variable unit delay VHDL modules are identical to the Simulink unit delay blocks in the DSP blockset. I would suggest when migrating a C function to VHDL, you may want to replace any if statements in C with generate statements in VHDL and then componentized the math to blocks that are stitched together with the generate statements. This will allow for a lot of flexibility and "playing" with the DSP algorithm with the synthesis tool over design resources. Note I believe the complex NCO will use the VHDL 93 version of the fixed-point package internally.

Scott D. Hoy
E-mail: scott.hoy@itt.com<mailto:scott.hoy@itt.com>

________________________________
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Daniel Kho
Sent: Monday, January 03, 2011 9:50 AM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Request for Input

Hi David and all,
I think that something like:
function zt ( var : <some type>
clock: std_ulogic;
reset: std_ulogic;
delay: Positive := 1;
enable: std_ulogic : ='1')
return <some type>;
might work. Might be something to play with.

The hope would be to let the synthesis tool figure out the divider style (given some constraints) and move the FFs back into the divider until timing is met.

Even better. With this, we could directly use functions and allow them to be clocked. My earlier suggestion of using functions to access processes is an indirect way to clock a function, and a workaround to this direct approach. If implementing this approach is possible in the standard, this would be even better than my earlier suggestion (of having that workaround).

Also, using a z-transform function to represent a clocked delay stage is a really cool idea (it really means what it says).

Maybe a attribute to set a default clock, reset and enable? Then it would look like:

Z'default_clock := clk;
Z'default_reset := rst;
Z'default_enable := '1';

Z : zt (x**2 / y, 15);

Here I'm assuming 15 z-transform delay stages are used (since we can't have time units in nanoseconds with are not synthesizable)? So, does this mean that it takes 15 clock cycles to implement this logic?

> Maybe a built in operator?
>
> Z <= x**2/y @ 15;

Well, maybe. Which clock, though?

Yes, brilliant. Or even, following the name of your z-transform function:
Z <= x**2/y zt 15;

Jonathan,
The clock is passed directly to the "zt" function. And I'm assuming that the attributes perform the mapping between the design's clock, reset, and enable signals to this function. So, I think what David is saying is this:

Top-level design:

--Maps top-level clocks, reset, and enable signals to the function. Similar to port-mapping.
--Here, the "Z" signal needs to be checked (by the compiler) to use the "zt" function, as in the expression above.
Z'clock := clk;
Z'reset := rst;
Z'enable := '1';

Package or separate VHDL file:
function zt ( var : <some type>
clock: std_ulogic;
reset: std_ulogic;
delay: Positive := 1;
enable: std_ulogic : ='1')
return <some type>;

Nice discussion, hope everyone enjoyed Christmas and the New Year!

Regards,
Daniel Kho

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