RE: [vhdl-200x] VHDL Testbench Enhancements

Hello all,

 

As for the verification language capability, I agree with Sukrit et. al.
that the core VHDL should not cover both hardware description and
hardware test/verification. I would suggest that if we were to decide
(perhaps due to competitive reasons) that we add verification features,
we add them as another VHDL extension, somewhat like VHDL-AMS, which is
not core VHDL, but just a VHDL extension that supports analog and
mixed-signal hardware description.

 

>> and multidimensional data types.

>To do.  Anything in particular you need?

What is meant by multidimensional data types? I think the present VHDL
can implement customized data types, which can be made multidimensional;
an example is creating an array of vectors, something like the
following:

type pipe4 is array (natural range <>) of std_logic_vector(3 downto 0);
--defined in a VHDL package

signal p:pipe4(15 downto 0);        -- defined in a VHDL architecture

 

where p is actually a group of 16x4 std_logic wires (16x4 2-dimensional
array of std_logic). I believe we can extend this to 3 or more
dimensions.

 

 

> 8) Object orientation

Where can I find any documentation on this effort? I would like to know
more about how this is being implemented. My view at present is that
this is not really necessary, as we already have a strong
entity-architecture syntax structure, which is very similar to object
orientation. Entities can be treated as objects in VHDL and can
communicate with one another (similar to objects talking to one another)
via I/O ports. The only issues are how to add another layer of
abstraction which defines the security of the attributes (or signals,
components, etc.) that are contained within the entity-architecture
body, somewhat like public, protected, or private attributes in
object-oriented languages.

 

Regards,

Daniel Kho

Altera Corporation

 

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jim Lewis
Sent: Tuesday, May 22, 2007 10:46 PM
To: sukrit shankar
Cc: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] VHDL Testbench Enhancements

 

Sukrit,

> I believe that testbench and verification related enhancements need
not 

> be made to VHDL., if the verification flow cannot be modeled so as to 

> have powerful links with the system level design flow. 

What kind of links do you need to system level design flow?

Are there things in the system space that you need the language

doing better?

 

What are you currently using for system design? Matlab?

There was a paper at MAPLD 06 on linking Matlab to the new

VHDL fixed point packages.  The abstract is at:

http://www.klabs.org/mapld06/abstracts/225_hoy_a.html

You can probably get the paper from Scott.

 

 

> However, the following features can be added to VHDL verification mode


> to make it somewhat better than likes of SystemVerilog.

> 1) Boolean, integer, real vector 

Done

 

> and multidimensional data types.

To do.  Anything in particular you need?

 

 > 8) Object orientation

Work in progress.

 

 > 5) Constrained random generation.

Work in progress

 

> 2) Associative arrays for holding sparse data

 > 4) FIFO s

 > 7) Loading and dumping memories.

Easy to implement with a class.  Prefer classes over

protected types due to extensibility.  I have prototypes

for these using protected types.

 

 > 10) Expected value detectors.

Scoreboards?  Another data structure that can be implemented

with classes.  I have a prototype using protected types.

Once we have classes in place we will need people to test

and/or build this.

 

> 3) The routines for basic queuing theory, such as fork and join.

Can you give a use model.  How do you communicate results (how

are return values connected back to something)?

 

> 6) Access to coverage data

As an API?  As attributes to named coverage objects?

 

> 9) Synchronization and handshaking

Building some of this into classes.  I think some of the

other parts are a matter of providing packages.

 

Cheers,

Jim

-- 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Jim Lewis

Director of Training             mailto:Jim@SynthWorks.com

SynthWorks Design Inc.           http://www.SynthWorks.com

1-503-590-4787

 

Expert VHDL Training for Hardware Design and Verification

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

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