Re: [vhdl-200x] VHDL Testbench Enhancements

Sukrit,
> I believe that testbench and verification related enhancements need not 
> be made to VHDL., if the verification flow cannot be modeled so as to 
> have powerful links with the system level design flow. 
What kind of links do you need to system level design flow?
Are there things in the system space that you need the language
doing better?

What are you currently using for system design? Matlab?
There was a paper at MAPLD 06 on linking Matlab to the new
VHDL fixed point packages.  The abstract is at:
http://www.klabs.org/mapld06/abstracts/225_hoy_a.html
You can probably get the paper from Scott.


> However, the following features can be added to VHDL verification mode 
> to make it somewhat better than likes of SystemVerilog.
> 1) Boolean, integer, real vector 
Done

> and multidimensional data types.
To do.  Anything in particular you need?

 > 8) Object orientation
Work in progress.

 > 5) Constrained random generation.
Work in progress

> 2) Associative arrays for holding sparse data
 > 4) FIFO s
 > 7) Loading and dumping memories.
Easy to implement with a class.  Prefer classes over
protected types due to extensibility.  I have prototypes
for these using protected types.

 > 10) Expected value detectors.
Scoreboards?  Another data structure that can be implemented
with classes.  I have a prototype using protected types.
Once we have classes in place we will need people to test
and/or build this.

> 3) The routines for basic queuing theory, such as fork and join.
Can you give a use model.  How do you communicate results (how
are return values connected back to something)?

> 6) Access to coverage data
As an API?  As attributes to named coverage objects?

> 9) Synchronization and handshaking
Building some of this into classes.  I think some of the
other parts are a matter of providing packages.

Cheers,
Jim
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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
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Expert VHDL Training for Hardware Design and Verification
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