RE: [vhdl-200x] VHDL Testbench Enhancements

 

>>ports. The only issues are how to add another layer of 
>>abstraction which defines the security of the attributes (or 
>>signals, components, etc.) that are contained within the 
>>entity-architecture body, somewhat like public, protected, or 
>>private attributes in object-oriented languages.

Daniel, 

re: OOP with VHDL

two other issues maybe three?

- methods (functions/tasks/procedures) that operate
on the objects

- inheritance (extensions of previously defined objects
into new objects, derived from the original)

- handles/pointers to objects 

I've seen linked list implementations in VHDL
so the third one can be done within the constraints
of the existing language, dont know about the 
first two.

An extension may be the way to go, without totally 
redefining the current language syntax.  So then which
language does one choose as an extension?  C++?, maybe
the System C flavor of it?  System Verilog?  Open Vera?
'E'?  

The way these languages currently tie into VHDL 
is left as an exercise for the EDA vendors to implement
and they're all different.  Perhaps the route is through
the current VHPI?


 -tim


Synopsys Inc.


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