[vhdl-200x] IP Protection and Encryption Donation

Cadence has graciously donated to the WG a specification for how IP can be encrypted and protected within VHDL. This proposal is based on the same fundamental capabilities as donated to the 1364 working group.

I have placed the PDF of the donation at: http://www.eda-twiki.org/vhdl-200x/docs/IP_donation_10.pdf <http://www.eda-twiki.org/vhdl-200x/docs/IP_donation_10.pdf>

Please review the donation and begin a discussion of its pros and cons. Also consider if the core capability should be recommended for separate standardization which the 1076 and 1364 working groups could then incorporate by reference. The advantages to such an organization of standardization would be to ensure both VHDL and Verilog use the same underlying capabilities and only differ in the syntactic realization of those capabilities in their respective languages. This would similar to SDF being a separate standard but used by both HDLs. Obviously, a single encryption mechanism for both languages would be advantageous to tool vendors. It would also make life incrementally easier for users who do mixed language design/verification.

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Stephen Bailey
ModelSim Verification TME
Mentor Graphics
sbailey@model.com
303-775-1655 (mobile, preferred)
720-494-1202 (office)
www.model.com <www.model.com>
Received on Tue May 18 08:13:25 2004