Re: [vhdl-200x] IP Protection and Encryption Donation

From: Ries, John <johnr@model.com>
Date: Tue May 18 2004 - 14:58:30 PDT

It seems to me the basic requirements for IP encryption are:

A) Provide a secure method of providing IP to VHDL tools so that
    they can do there work, i.e. simulation and synthesize, without
    providing to the customer how the IP works.

B) Allow for the same IP to work in tools from different vendors
    without having to provide multiple copies of the IP. The current verilog
    `protected is different for each vendor.

C) Allow the IP provider to control who has access, not just everyone
    that owns the specific tool.

The Cadence document seams to address C well. I don't think it addresses
A and B very well.

I don't believe there is sufficient depth in how data is represent in the
data_block, key_block, and digest_block, to allow one vendor tool's
to read blocks generated by another vendor's tool. Specifically there is
no text describing how result of the encryption is converted into the text stream
within the data, key, and digest blocks. Maybe this is part of the encryption
algorithms themselves. If it is then this comment is moot.

As for providing hiding of IP from the user, the document does say anything
about a number of items.

1) Does the VHPI have access to encrypted models.
2) If error/assertions occur within the encrypted model can
    the tool report a pathname to an object in the model?
3) If part of the hierarchy is encrypted, what does the `path_name
    attribute return. Can on use the `path_name attribute in
    an encrypted portion? What does it return?
4) Can SDF be applied to an encrypted model.
5) Is direct visibility effected by an encrypted model?
6) Can configurations be applied to an encrypted model?
7) This is an implementation question, but most vendors have
    tools that allow for inspection of libraries, do they show encrypted
    design unit names decrypted?
8) Is single stepping allowed within an encrypted model?

Regards,
   John

Bailey, Stephen wrote:
> Cadence has graciously donated to the WG a specification for how IP can be encrypted and protected within VHDL. This proposal is based on the same fundamental capabilities as donated to the 1364 working group.
>
> I have placed the PDF of the donation at: http://www.eda-twiki.org/vhdl-200x/docs/IP_donation_10.pdf <http://www.eda-twiki.org/vhdl-200x/docs/IP_donation_10.pdf>
>
> Please review the donation and begin a discussion of its pros and cons. Also consider if the core capability should be recommended for separate standardization which the 1076 and 1364 working groups could then incorporate by reference. The advantages to such an organization of standardization would be to ensure both VHDL and Verilog use the same underlying capabilities and only differ in the syntactic realization of those capabilities in their respective languages. This would similar to SDF being a separate standard but used by both HDLs. Obviously, a single encryption mechanism for both languages would be advantageous to tool vendors. It would also make life incrementally easier for users who do mixed language design/verification.
>
> ------------
> Stephen Bailey
> ModelSim Verification TME
> Mentor Graphics
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com <www.model.com>

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Received on Tue May 18 14:58:39 2004

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