Subject: Re: [vhdl-200x] re: Read variable before WRITE
From: VhdlCohen@aol.com
Date: Thu Dec 18 2003 - 08:04:31 PST
In a message dated 12/18/2003 6:06:55 AM Pacific Standard Time,
e.molenkamp@utwente.nl writes:
Ben,
I don't agree. If you have simulated your design it is not nice that the tool
reports only with a warning if there is a mismatch between synthesis and
simulation.
If the synthesis tool can not synthesize it it is no problem. But it should
report with an error; maybe: "ERROR: variable B is read before assigned; not
supported for synthesis".
(maybe not exact enough, since it is allowed in a sequential process).
Also in the synthesis standard 1076.6 there is a subset of VHDL defined that
a variable should be assigned a vlaue before it is written in combinational
logic.
...
Agreed, it should report an error. I am in the process of twisting his arm!
From the vendor:
<Hi Ben,
Thanks for your feedback. I do not think that the synthesis tool should error
out on encountering this VHDL description. But, as you had suggested, a
warning message may be more appropriate here. I have discussed this with R&D and
have filed an enhancement request for the same. The bug number for your
reference is 1xxxxxx.
Best Regards,
synthesis vendor >
Thanks,
Ben
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