RE: [vhdl-200x] re: Read variable before WRITE

Subject: RE: [vhdl-200x] re: Read variable before WRITE
From: Tim Schneider (Tim.Schneider@synopsys.com)
Date: Tue Jan 06 2004 - 15:46:07 PST

• Next message: Jonathan Bromley: "RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g"
• Previous message: Marcus Harnisch: "Re: [vhdl-200x] A 2nd proposal to boolean equivalence"
• Maybe reply: Tim Schneider: "RE: [vhdl-200x] re: Read variable before WRITE"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

FYI

Some outputs from Design Compiler (version 2003.06-SP1)

test.vhdl (orig. file)
vhdl_tst.log (dc log file)
test_mapped.vhdl
test_mapped.v

mapped DC output files.. (i.e. after synthesis)

  -tim

• application/octet-stream attachment: vhdl_tst.log

• application/octet-stream attachment: test_mapped.vhdl

• application/octet-stream attachment: test.vhdl

• application/octet-stream attachment: test_mapped.v

• Next message: Jonathan Bromley: "RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g"
• Previous message: Marcus Harnisch: "Re: [vhdl-200x] A 2nd proposal to boolean equivalence"
• Maybe reply: Tim Schneider: "RE: [vhdl-200x] re: Read variable before WRITE"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Tue Jan 06 2004 - 15:49:23 PST