Subject: [vhdl-200x] re: Read variable before WRITE
From: VhdlCohen@aol.com
Date: Tue Dec 16 2003 - 21:20:42 PST
Jim,
I transferred the model that you wrote to a synthesis vendor. Below is his
response, which may appear to be vendor independent:
I do see the mismatch in simulation between the RTL netlist and the post
synthesized netlist. The problem here is that the synthesis tool does not have the
concept of a delta delay between scheduled events. As a result the value of a
variable is immediately available to a signal assignment within the process.
Also note that a process in VHDL that describes combinatorial logic is always
active when synthesized. Whereas in the case of simulation the described logic
is active only when there is a change in one of the signals in the
sensitivity list. Thus, a small delta delay between scheduled events in simulation may
lead to a different output value until the sensitivity list is activated again.
I have run the design through some verification tools, and the gate level
netlist appears to be equivalent. In general this is not a good coding practice
when describing logic in VHDL for synthesis. I would like to know what the user
expects to be generated from the described logic.
My assessment of that is that we should NOT state that " if a synthesis
tool produces results that simulate differently for rtl and gate simulations,
then the
synthesis tool is non-compliant". This is because the synthesis engine
operates differently than simulation.
Instead, I recommend that we state:
" if a synthesis tool produces results that simulate differently for rtl and
gate simulations, then the synthesis tool should report this disparity as a
warning".
Below is discussion on the vhdl synthesis reflector: The attached code will
not simulate the same in gate level model as RTL model.
My read on section 5 says that if a synthesis
tool produces results that simulate differently
for rtl and gate simulations, then the
synthesis tool is non-compliant.
Jim,
Correct. FYI, I tried your code with a synthesis vendor, and I got the same
result as if the variable was written before it was read. I'll inform that
vendor of that error, and will forward any reply.
But, you're correct, it should be an error. I guess vendors get "smart" and
aim at user's "intent". If other want to experiment with synthesis tools
and report on the result, below is the test code:
library ieee;
use ieee.std_logic_1164.all;
entity strangev is
port (
a : in std_logic;
b : in std_logic;
d : in std_logic;
y : out std_logic);
end entity strangev;
architecture rtl of strangev is
begin -- architecture rtl
StrangeProc : process (A, B, D)
variable C : std_logic;
begin
Y
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