Subject: RE: [vhdl-200x] re: Read variable before WRITE
From: Bailey, Stephen (SBailey@model.com)
Date: Thu Dec 18 2003 - 07:52:44 PST
Ben,
I don't agree. If you have simulated your design it is not nice that the
tool reports only with a warning if there is a mismatch between
synthesis and simulation.
If the synthesis tool can not synthesize it it is no problem. But it
should report with an error; maybe: "ERROR: variable B is read before
assigned; not supported for synthesis".
(maybe not exact enough, since it is allowed in a sequential process).
Also in the synthesis standard 1076.6 there is a subset of VHDL defined
that a variable should be assigned a vlaue before it is written in
combinational logic.
I have not yet an idea how I would synthesize the specification you have
send to the tool vendor.
The synthesis tool I use also generates a wrong citrcuit, even without
any warning.
Since the example was not restricted to the "synthesisable subset" I
added an simplified example also not restricted to the synthesis subset:
- initial value for b
- variable b is assigned before it is read.
The synthesis tool, that generates an incorrect circuit, would probable
insert a wire between A and Y.
However a synthesis tool that generates a correct circuit inserts an
inverter between A and Y. (I added z<=not a for comparison.)
Maybe you can send this example to the tool vendor and hopefully that
tool will do a better job (reporting an error, or synthesize a correct
circuit) and others will follow :-).
entity funny is
port (a : in bit;
y : out bit;
z : out bit);
end entity funny;
architecture test of funny is
begin
process(a) is
variable b : bit := '1';
begin
y <= b;
b := a;
end process;
z <= not a;
end architecture test;
Egbert Molenkamp
-----Oorspronkelijk bericht-----
Van: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] Namens
VhdlCohen@aol.com
Verzonden: woensdag 17 december 2003 6:21
Aan: Jim@synthworks.com; vhdl-200x@eda.org
Onderwerp: [vhdl-200x] re: Read variable before WRITE
Jim,
I transferred the model that you wrote to a synthesis vendor. Below is
his response, which may appear to be vendor independent:
I do see the mismatch in simulation between the RTL netlist and the post
synthesized netlist. The problem here is that the synthesis tool does
not have the concept of a delta delay between scheduled events. As a
result the value of a variable is immediately available to a signal
assignment within the process. Also note that a process in VHDL that
describes combinatorial logic is always active when synthesized. Whereas
in the case of simulation the described logic is active only when there
is a change in one of the signals in the sensitivity list. Thus, a small
delta delay between scheduled events in simulation may lead to a
different output value until the sensitivity list is activated again.
I have run the design through some verification tools, and the gate
level netlist appears to be equivalent. In general this is not a good
coding practice when describing logic in VHDL for synthesis. I would
like to know what the user expects to be generated from the described
logic.
My assessment of that is that we should NOT state that " if a synthesis
tool produces results that simulate differently for rtl and gate
simulations, then the
synthesis tool is non-compliant". This is because the synthesis engine
operates differently than simulation.
Instead, I recommend that we state:
" if a synthesis tool produces results that simulate differently for
rtl and gate simulations, then the synthesis tool should report this
disparity as a warning".
Below is discussion on the vhdl synthesis reflector: The attached code
will
not simulate the same in gate level model as RTL model.
My read on section 5 says that if a synthesis
tool produces results that simulate differently
for rtl and gate simulations, then the
synthesis tool is non-compliant.
Jim,
Correct. FYI, I tried your code with a synthesis vendor, and I got the
same
result as if the variable was written before it was read. I'll inform
that
vendor of that error, and will forward any reply.
But, you're correct, it should be an error. I guess vendors get "smart"
and
aim at user's "intent". If other want to experiment with synthesis
tools
and report on the result, below is the test code:
library ieee;
use ieee.std_logic_1164.all;
entity strangev is
port (
a : in std_logic;
b : in std_logic;
d : in std_logic;
y : out std_logic);
end entity strangev;
architecture rtl of strangev is
This archive was generated by hypermail 2b28 : Thu Dec 18 2003 - 07:54:14 PST