Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003
From: Bailey, Stephen (SBailey@model.com)
Date: Thu Dec 18 2003 - 07:56:47 PST
Hi Scott,
Your suggestion would be an option. Assuming the proposed context clause becomes part of VHDL, the impact of always using one more package is minimal.
I can't think of any other negative to the proposal. The obvious positive is that people that don't want it, shouldn't get it by accident.
-Steve Bailey
-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf Of Scott Thibault
Sent: Thursday, December 18, 2003 8:45 AM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003
Is there some reason that the equivalence operator needs to be defined in std_logic_1164? Would it be less objectionable if it were in another package like std_logic_bool or something like that? That way the user would need to explicitly request it.
--Scott Thibault
Green Mountain
Computing Systems, Inc.
http://www.gmvhdl.com <http://www.gmvhdl.com/>
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