Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003

Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Dec 17 2003 - 07:19:24 PST

• Next message: Bailey, Stephen: "RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003"
• Previous message: Jim Lewis: "ANDY: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003"
• In reply to: Andy D Jones: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Next in thread: Steve Casselman: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Next in thread: Bailey, Stephen: "RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003"
• Reply: Jim Lewis: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Andy,
Please post an example where you think this would be a problem.
COND is only for conditionals. Overloading of operators
will apply to all expressions.

Regards,
Jim

Andy D Jones wrote:

> This slope is getting slippery...! First we said this would only be in
> conditionals, now we're going to extend it to expressions? Where will
> it be next? Why not just abandon strong typing altogether and "let the
> compiler figure out what we meant"?
>
> This perfectly illustrates why I think it is a bad idea: when users
> start to ask "Why can I get away with this here, but not there?" and we
> don't have a good answer, then we'll be chipping more and more out of
> the guts of vhdl 'till it looks and functions like verilog.
>
> Wrong direction guys!
>
> Andy Jones
> Lockheed Martin
> Missiles & Fire Control
> Dallas TX
> andy.d.jones@lmco.com
>
> Jim Lewis wrote:
>
>> Marcus,
>> If we limit boolean conversion to being only applied
>> at the top most level then we need to provide the following
>> overloading to logic operators to make it generally useful:
>> L R return
>> sul bool bool
>> bool sul bool
>> bit bool bool
>> bool bit bool
>>
>> Cheers,
>> Jim
>>
>>
>> Marcus Harnisch wrote:
>>
>>> Jim,
>>>
>>> Jim Lewis writes:
>>> > 2) if clk and clk'event then -- W/ the implicit boolean
>>> conversion
>>>
>>> Did I miss anything? I was under the impression that the implicit
>>> boolean conversion will only be wrapped around the condition. Here you
>>> are giving an example where an implicit conversion is applied on the
>>> left argument to "and".
>>>
>>> Best regards,
>>> Marcus
>>>
>>>
>>>
>>

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

• Next message: Bailey, Stephen: "RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003"
• Previous message: Jim Lewis: "ANDY: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003"
• In reply to: Andy D Jones: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Next in thread: Steve Casselman: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Next in thread: Bailey, Stephen: "RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003"
• Reply: Jim Lewis: "Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Wed Dec 17 2003 - 07:20:53 PST