Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003
From: Steve Casselman (sc@vcc.com)
Date: Wed Dec 17 2003 - 09:44:35 PST
Isn't the problem that this conversion is an implicit one? Why not have it be explicet with a bool attribute? H'bool for example. The 'bool attribute could be defined for each type.
Steve
----- Original Message -----
From: Andy D Jones
To: Jim Lewis
Cc: vhdl-200x@eda.org
Sent: Wednesday, December 17, 2003 7:03 AM
Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4, 2003
This slope is getting slippery...! First we said this would only be in conditionals, now we're going to extend it to expressions? Where will it be next? Why not just abandon strong typing altogether and "let the compiler figure out what we meant"?
This perfectly illustrates why I think it is a bad idea: when users start to ask "Why can I get away with this here, but not there?" and we don't have a good answer, then we'll be chipping more and more out of the guts of vhdl 'till it looks and functions like verilog.
Wrong direction guys!
Andy Jones
Lockheed Martin
Missiles & Fire Control
Dallas TX
andy.d.jones@lmco.com
Jim Lewis wrote:
Marcus,
If we limit boolean conversion to being only applied
at the top most level then we need to provide the following
overloading to logic operators to make it generally useful:
L R return
sul bool bool
bool sul bool
bit bool bool
bool bit bool
Cheers,
Jim
Marcus Harnisch wrote:
Jim,
Jim Lewis writes:
> 2) if clk and clk'event then -- W/ the implicit boolean conversion
Did I miss anything? I was under the impression that the implicit
boolean conversion will only be wrapped around the condition. Here you
are giving an example where an implicit conversion is applied on the
left argument to "and".
Best regards,
Marcus
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