Subject: ANDY: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Dec 17 2003 - 07:13:00 PST
Andy,
This code is dangerous as currently some synthesis tools
may produce a register, but others ignore the sensitivity
list and create a latch. It is not portable.
> main: process (clk)
> begin
> if clk = '1' then -- means rising edge clock
> do_rising_edge_stuff(inputs, outputs);
> end if;
> end process;
I caution you away from this coding style as
you will run into problems when you synthesize on
different synthesis tools.
The COND operator has no effect on edge semantics.
In your examples the edge implication comes from
the sensitivity list.
What you are saying regarding the clock and enable is
not true for registers as only clk is on the sensitivity
list. Your concerns are true for latches, which requres
all signals read in a process to be on the sensitivity list.
The following code
1) IS NOT PORTABLE BETWEEN SYNTHESIS TOOLS
2) May create register with load enable.
> main: process (clk)
> begin
> if clk and enable then -- = rising_edge(clk and enable) = gated clock,
> not clock enable!
> do_rising_edge_stuff(inputs, outputs);
> end if;
> end prodess;
> like using component definitions/configurations/instantiations
> instead of entity instantiation.
Last I checked some synthesis vendors do not support entity
instantiation. This is why I show it, but don't focus on it
in my classes as the place I would recommend using it, it is not
permitted to be used.
> Like using std_logic and std_logic_vector everywhere
> when integer and boolean are simpler, easier to read and write, and
> faster to simulate.
If you use an integer as a port, what direction are the bits that
result in the implementation.
For signed math:
signal A, B, Y : integer range -8 to 7 ;
-- What do you need to add here to get Y in the correct range?
Should it clip or should it modulo?
Y <= A + B ;
> The proposed implicit call to COND is a terrible idea,
> providing precious little benefit for a monumental loss in clarity.
If done right it will work well.
The only way it will get in the language is if it is done right.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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