Subject: Re: [vhdl-200x], vital issues
From: Ajayharsh Varikat (firstname.lastname@example.org)
Date: Mon Mar 17 2003 - 08:36:17 PST
>> The real question is did Vital hamstring VHDL simulation speed to the point
>> were engineers _have_ to use Verilog to get their work done in a timely
>> fashion? If that is the case then why not have a "gate level VHDL" format?
>> Of course this would be structural VHDL linked against a simple non-Vital
>> library that can be simulated as fast or faster than gate level Verilog. Let
>> vendors output someone's Verilog work in "gate level VHDL." This way every
>> other entry system would be able to get the same benifits. We could call it
>> SuperSpeed VHDL or some such thing.
This assumes that defining a new simplified gate level standard is all
it takes to get improved performance. I would disagree. Verilog gates
simulate fast mainly because of the significant effort that has gone into
accelerating them. Speeding up a new VHDL format would require similar
optimizations, which could erode a lot of the perceived cost advantage.
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