Subject: Re: [vhdl-200x], vital issues
From: Rick Munden (email@example.com)
Date: Fri Mar 14 2003 - 13:31:06 PST
Jim Lewis wrote:
> Steve Casselman wrote:
>> The real question is did Vital hamstring VHDL simulation speed to the
>> were engineers _have_ to use Verilog to get their work done in a timely
> According to a paper at DVCon, Verilog gates are 4x faster than
> VHDL gates.
That may be true but I would want to verify it before believing it.
Plus, anyone can write slow code.
>> If that is the case then why not have a "gate level VHDL" format?
> This sounds great.
> My thought is that with economic forces at play, it sure would
> be nice for silicon vendors (and perhaps eda vendors too) if
> the VHDL format were some how compatible with the Verilog
> gate level format. This way they only need to support one
> sign-off quality gate level netlist.
I thought it was a language, not just a format.
> > We could call it SuperSpeed VHDL ...
> Perhaps I set my targets too low when I thought of matching
> the speed of Verilog gates. However, you sparked some ideas.
> What do we use gate level simulations for these days?
> I use static timing analysis to figure out how fast the chip
> runs. I use gate sims to find issues between RTL and gate
> (reset, ...) and as a sanity check on my timing assumptions
> made in static timing analysis. I am sure there are more.
> With some assumptions, perhaps we can even add modes to
> run gate sims without timing enabled and run considerably
VITAL supports turning off timing checks. Simulators support it. Don't
do the backannotation and you get unit delays. I've tried these things
and haven't found that much difference in performance though.
> Still I think we would all benefit if the base level library
> format were either based on or easily translatable
> from a Verilog library.
It seems like you are assuming that one simulator that runs both
languages is going to be less expensive than two simulators. I have not
heard any of the EDA vendors weigh in on that point. It would be
somewhat cheaper for the ASIC vendors to support just one library. It
would cost them more than half as much, as they usually develop in one
language and generate the other.
What I would like to hear is a discussion of why VITAL is slower than
Verilog for gate-level simulation.
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